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Mongoose 3 µarch
General Info
Arch Type	CPU
Designer	Samsung
Manufacturer	Samsung
Introduction	2018
Process	10 nm
Core Configs	4
Pipeline
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Decode	6-way
Instructions
ISA	ARMv8
Succession
Mongoose 2 Mongoose 4

Mongoose 3 (M3) is an ARM microarchitecture designed by Samsung for their consumer electronics serving as a successor to the Mongoose 2.

Process Technology

The M3 was fabricated on Samsung's second generation 10LPP (Low Power Plus) process.

Compiler support

Compiler	Arch-Specific	Arch-Favorable
GCC	-march=armv8-a+crypto	-mtune=exynos-m3

Architecture

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Mongoose 1/M2

• 10nm 10LPP process (from 1st gen 10LPP)
• Core
  • Front-end
    • larger instruction queue (40 entries, up from 24)
    • 6-way decode (from 4)
    • µOP fusion
      • new fuse address generation and memory µOP support
      • new fuse literal generation µOP support
  • Back-end
    • Larger ReOrder buffer (228 entries, from 96 entries)
    • New fastpath logical shift of up to 3 places
    • Larger dispatch window (12 µOP/cycle, from 9)
    • Larger Integer physical register file
    • Larger FP physical register
    • Integer cluster
      • 9 pipes (from 7)
        • New pipe for a second load unit added
        • New pipe for a second ALU with 3-operand support and MUL/DIV
        • Double throughput for most integer operations
    • Floating Point cluster
      • 3 pipes (From 3)
        • Throughput of most FP operation have increased by 50% or doubled
        • Additional EUs
          • crypto EU, simple vector EU, vector shuffle/shift/mul, new FP store, new FP conversion
  • Memory subsystem
    • New L3 Cache
      • 4 MiB
    • 2x bandwidth (32B (2x16B)/cycle from 16B/cycle)
      • fast paired 128-bit loads and stores
• branch misprediction penalty increased (16 cycles, from 14)

This list is incomplete; you can help by expanding it.

Block Diagram

Individual Core

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Memory Hierarchy

This section is empty; you can help add the missing info by editing this page.

Core

This section is empty; you can help add the missing info by editing this page.

All M3 Processors

	List of M3-based Processors
	Main processor						Integrated Graphics
Model	Family	Launched	Arch	Cores	Frequency	Turbo	GPU	Frequency
Count: 0

References

• LLVM: lib/Target/AArch64/AArch64SchedExynosM3.td