From WikiChip
ARMADA 628 - Marvell
< marvell‎ | armada
Revision as of 16:03, 24 January 2018 by 92.113.211.174 (talk) (→‎Graphics)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Edit Values
ARMADA 628
armada 628.png
General Info
DesignerMarvell
ManufacturerTSMC
Model Number628
Part Number88AP628
MarketMobile
IntroductionSeptember 23, 2010 (announced)
March, 2011 (launched)
General Specs
FamilyARMADA 600
Series600
Frequency1,500 MHz, 624 MHz
Microarchitecture
ISAARMv6 (ARM), ARMv5
MicroarchitectureSheeva PJ4
PlatformARMADA
Core NameSheeva PJ4
Process55 nm
Word Size32 bit
Cores3
Threads3
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
VI/O1.5 V ± 0.3 V, 3.0 V, 3.3 V

ARMADA 628 was a 32-bit tri-core ARM microprocessor introduced by Marvell in 2011. This processor, which is based on Marvell's Sheeva PJ4 microarchitecture, operated at 1.5 GHz for the 2 big cores with lower frequency for the third low-power core. The 628 supported up to 2 GiB of DDR3-1066 memory and integrated a Vivante GC1000 IGP.

The ARMADA 628 featured three heterogeneous cores - two identical large powerful cores operating at 1.5 GHz each with a third lower power core which operated at just 624 MHz whenever lightweight work was done which helped save power.

Cache

Main article: Sheeva PJ4 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L1D$96 KiB
98,304 B
0.0938 MiB
3x32 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-800
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Max Bandwidth7.942 GiB/s
8,132.608 MiB/s
8.528 GB/s
8,527.658 MB/s
0.00776 TiB/s
0.00853 TB/s
Bandwidth
Single 7.942 GiB/s

Static Memory Controller

  • 4 chip selects, up to 256 MB each
  • Asynch/Sync operation up to 78 MHz
  • A/D and AA/D Mode, x8 & x16 NOR Flash interface
  • Support for VLIO or companion chips

NAND Flash Controller

  • ONFI compliant controller supporting SLC and MLC NAND, x8 & x16, small block and large block
  • 2 Chip Selects with up to 64GB of address space
  • Support for 2 KB and 4 KB page sizes
  • 2-bit detect/1-bit correct ECC & 16-bit correct BCH

MMC, SD and SDIO Controller

  • 4x MMC/SD/SDIO/CE-ATA Controllers
  • Supports MMC/eMMC v4.2, 4.3 and 4.4
  • SDIO v 2.0, SDcard v2.1 and v3.0 (UHS-I)
  • CE-ATA 1/4/8-Bit, SPI mode and boot suppor

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports3
Features2x HSIC, 1x FSIC/12pin ULPI
UART
Ports4
I²C
Ports6
JTAGYes


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUGC1000
DesignerVivante
Frequency500 MHz
0.5 GHz
500,000 KHz
OutputHDMI, DSI
Max Resolution
HDMI1920x1080
DSI1920x1080
Standards
DirectX11
OpenGL3.0
OpenCL1.2
OpenGL ES3.1
  • 1080p decode support for H.264 high profile, VC-1/WMV, MPEG-4, MPEG-2, H.263, On2 VP8.
  • 1080p encode support for h.264 high profile, MPEG-4, MPEG-2, H.263 and On2 VP8

Hardware Accelerators

Marvell Wireless Trusted Module v3

  • Hashing units: MD5, SHA-1, HMAC-SHA-1; SHA-224/SHA256 and HMAC, SHA-512 and HMAC, MD5 and HMAC-MD5
  • Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC4
  • Asymmetric crypto: ECC (Prime field ECC, FIPS std curve EC-224/256, EC-DSA) & RSA (RSA key gen, PKCS#1 v1.5/v2.1 Digital Signatures, x.509 Digital Certificate), & DiffieHellman Key exchange. True HW RNG, FIPS 140-2 certification

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
VFPv3-D16Vector Floating Point (VFP) v3 (16 Regs) Extension
NEONAdvanced SIMD extension
WMMXWireless MMX
WMMX 2Wireless MMX 2
Retrieved from "https://en.wikichip.org/w/index.php?title=marvell/armada/628&oldid=73059"
Facts about "ARMADA 628 - Marvell"
RDF feed
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) + and 624 MHz (0.624 GHz, 624,000 kHz) +
core count3 +
core nameSheeva PJ4 +
designerMarvell +
familyARMADA 600 +
first announcedSeptember 23, 2010 +
first launchedMarch 2011 +
full page namemarvell/armada/628 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuGC1000 +
integrated gpu base frequency500 MHz (0.5 GHz, 500,000 KHz) +
integrated gpu designerVivante +
io voltage1.5 V (15 dV, 150 cV, 1,500 mV) +, 3 V (30 dV, 300 cV, 3,000 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
io voltage tolerance0.3 V +
isaARMv6 + and ARMv5 +
isa familyARM +
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ size96 KiB (98,304 B, 0.0938 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateMarch 2011 +
main imageFile:armada 628.png +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory bandwidth7.942 GiB/s (8,132.608 MiB/s, 8.528 GB/s, 8,527.658 MB/s, 0.00776 TiB/s, 0.00853 TB/s) +
max memory channels1 +
microarchitectureSheeva PJ4 +
model number628 +
nameARMADA 628 +
part number88AP628 +
platformARMADA +
process55 nm (0.055 μm, 5.5e-5 mm) +
series600 +
smp max ways1 +
supported memory typeDDR3-1066 + and DDR2-800 +
thread count3 +
word size32 bit (4 octets, 8 nibbles) +