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FastMATH-LP
General Info
Designer	Intrinsity
Manufacturer	TSMC
Model Number	FastMATH-LP
Market	Embedded
Introduction	2002 (announced) 2003 (launched)
General Specs
Family	FastMATH
Frequency	1,000 MHz
Bus type	RapidIO
Bus speed	500 MHz
Bus rate	4 GT/s
Microarchitecture
Microarchitecture	FashMATH
Process	130 nm
Technology	Dynamic CMOS
Word Size	32 bit
Cores	1
Threads	1
Max Memory	1 GiB
Electrical
Power dissipation	6 W
Vcore	0.85 V

The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.

Cache

Main article: FastMATH § Cache

Cache Info [Edit Values]
L1I$	16 KiB 16,384 B 0.0156 MiB	1x16 KiB 256 blocks × 16 words/block
L1D$	16 KiB 16,384 B 0.0156 MiB	1x16 KiB 256 blocks × 16 words/block write-through or write-back mode
L2$	1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB	1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR-400
Controllers	1
Channels	2
Max memory	1 GB

Matrix and Vector Unit

• SIMD architecture
• Operates on 4x4 array of 32-bit elements
• Fixed-point matrix, vector, and scalar data types

Features

• JTAG interface
• 8-bit or 32-bit wide bus operates up to 66 MHz

Documents

Manuals

• FastMATH Product Brief