Xeon E3-1260L v5 - Intel

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	Xeon E3-1260L v5
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	E3-1260L v5
Part Number	CM8066201921903
S-Spec	SR2CR, SR2LH
Market	Server
Introduction	October 19, 2015 (announced); October 19, 2015 (launched)
Release Price	$294
Shop	Amazon
	General Specs
Family	Xeon E3
Series	E3-1200 v5
Locked	Yes
Frequency	2,900 MHz
Turbo Frequency	Yes
Turbo Frequency	3,900 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	29
CPUID	506E3
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake
Platform	Greenlow
Chipset	Sunrise Point
Core Name	Skylake DT
Core Family	6
Core Model	94
Core Stepping	R0
Process	14 nm
Technology	CMOS
Die	122 mm²
Word Size	64 bit
Cores	4
Threads	8
Max Memory	64 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
Vcore	0.55 V-1.52 V
TDP	45 W
Tjunction	0 °C – 100 °C
Tstorage	-25 °C – 125 °C
	Packaging
Dimension	37.5 mm x 37.5 mm x 4.4 mm
Pitch	0.914 mm
Contacts	1151
Socket	LGA-1151

Xeon E3-1260L v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 2.9 GHz with turbo boost of 3.9 GHz. The E3-1260L v5 is a special low-power chip with a TDP of 45 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has no integrated graphics processor.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	4-way set associative	write-back

L3$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		4x2 MiB		write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR3L-1600, DDR4-2133
Supports ECC	Yes
Max Mem	64 GiB
Controllers	1
Channels	2
Max Bandwidth	31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s
Bandwidth	Single 15.89 GiB/s Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	16
Configs	1x16, 2x8, 1x8+2x4

Graphics

This chip has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
SGX	Software Guard Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon E3-1260L v5 - Intel#package + and Xeon E3-1260L v5 - Intel#io +
base frequency	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Sunrise Point +
clock multiplier	29 +
core count	4 +
core family	6 +
core model	94 +
core name	Skylake DT +
core stepping	R0 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
cpuid	506E3 +
designer	Intel +
die area	122 mm² (0.189 in², 1.22 cm², 122,000,000 µm²) +
family	Xeon E3 +
first announced	October 19, 2015 +
first launched	October 19, 2015 +
full page name	intel/xeon e3/e3-1260l v5 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard +
has intel enhanced speedstep technology	true +
has intel secure key technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate	October 19, 2015 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Skylake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	E3-1260L v5 +
name	Xeon E3-1260L v5 +
package	FCLGA-1151 +
part number	CM8066201921903 +
platform	Greenlow +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 294.00 (€ 264.60, £ 238.14, ¥ 30,379.02) +
s-spec	SR2CR + and SR2LH +
series	E3-1200 v5 +
smp max ways	1 +
socket	LGA-1151 +
supported memory type	DDR3L-1600 + and DDR4-2133 +
tdp	45 W (45,000 mW, 0.0603 hp, 0.045 kW) +
technology	CMOS +
thread count	8 +
turbo frequency (1 core)	3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

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