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Core m5-6Y57 - Intel
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Core m5-6Y57 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | m5-6Y57 |
Part Number | HE8066201922876 |
S-Spec | SR2EG |
Market | Mobile |
Introduction | September 1, 2015 (announced) September 27, 2015 (launched) |
Release Price | $281 |
Shop | Amazon |
General Specs | |
Family | Core m5 |
Series | m-6Y |
Locked | Yes |
Frequency | 1100 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 2,800 MHz (1 core), 2,400 MHz (2 cores) |
Bus type | DMI 3.0 |
Clock multiplier | 11 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake |
Platform | Skylake |
Core Name | Skylake Y |
Core Family | 6 |
Core Model | 78 |
Core Stepping | D1 |
Process | 14 nm |
Transistors | 1,750,000,000 |
Technology | CMOS |
Die | 98.57 mm² 10.3 mm × 9.57 mm |
MCP | Yes (2 dies) |
Word Size | 64 bit |
Cores | 2 |
Threads | 4 |
Max Memory | 16 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
SDP | 3 W |
TDP | 4.5 W |
cTDP down | 3.5 W |
cTDP down frequency | 600 MHz |
cTDP up | 7 W |
cTDP up frequency | 1500 MHz |
Tjunction | 5 °C – 100 °C |
Packaging | |
Template:packages/intel/fcbga-1515 |
Core M5-6Y57 is an ultra-low power 64-bit dual-core x86 microprocessor introduced by Intel in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.8 GHz. This chip, which is manufactured on a 14 nm process, is based on the Skylake microarchitecture. The Core M5-6Y57 incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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[Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
VP9 | ✘ | 0 | Unified | 2160p (4K) |
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Drivers
Facts about "Core m5-6Y57 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core m5-6Y57 - Intel#io + |
base frequency | 1,100 MHz (1.1 GHz, 1,100,000 kHz) + |
bus type | DMI 3.0 + |
clock multiplier | 11 + |
core count | 2 + |
core family | 6 + |
core model | 78 + |
core name | Skylake Y + |
core stepping | D1 + |
designer | Intel + |
device id | 0x191E + |
die area | 98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) + |
die count | 2 + |
die length | 10.3 mm (1.03 cm, 0.406 in, 10,300 µm) + |
die width | 9.57 mm (0.957 cm, 0.377 in, 9,570 µm) + |
drivers url | https://downloadcenter.intel.com/product/94026 + |
family | Core m5 + |
first announced | September 1, 2015 + |
first launched | September 27, 2015 + |
full page name | intel/core m/m5-6y57 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Stable Image Platform Program + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel stable image platform program support | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics 515 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | September 27, 2015 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
max memory bandwidth | 27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 10 + |
microarchitecture | Skylake + |
min junction temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
model number | m5-6Y57 + |
name | Core m5-6Y57 + |
part number | HE8066201922876 + |
platform | Skylake + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 281.00 (€ 252.90, £ 227.61, ¥ 29,035.73) + |
s-spec | SR2EG + |
sdp | 3 W (3,000 mW, 0.00402 hp, 0.003 kW) + |
series | m-6Y + |
smp max ways | 1 + |
supported memory type | LPDDR3-1866 + and DDR3L-1600 + |
tdp | 4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) + |
tdp down | 3.5 W (3,500 mW, 0.00469 hp, 0.0035 kW) + |
tdp down frequency | 600 MHz (0.6 GHz, 600,000 kHz) + |
tdp up | 7 W (7,000 mW, 0.00939 hp, 0.007 kW) + |
tdp up frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 1,750,000,000 + |
turbo frequency (1 core) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
turbo frequency (2 cores) | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |