Edit Values |
Core i3-2377M |
|
Designer | Intel |
Manufacturer | Intel |
Model Number | i3-2377M |
Part Number | AV8062701048004 |
S-Spec | SR0CW |
Market | Mobile |
Introduction | September, 2012 (announced) September, 2012 (launched) |
Release Price | $250 |
Shop | Amazon |
|
Family | Core i3 |
Series | i3-2000 |
Locked | Yes |
Frequency | 1,500 MHz |
Bus type | DMI 2.0 |
Bus rate | 4 × 5 GT/s |
Clock multiplier | 15 |
CPUID | 0x206A7 |
|
ISA | x86-64 (x86) |
Microarchitecture | Sandy Bridge |
Platform | Sandy Bridge M |
Chipset | Cougar Point |
Core Name | Sandy Bridge M |
Core Family | 6 |
Core Model | 42 |
Core Stepping | J1 |
Process | 32 nm |
Transistors | 624,000,000 |
Technology | CMOS |
Die | 149 mm² |
Word Size | 64 bit |
Cores | 2 |
Threads | 4 |
Max Memory | 16 GiB |
|
Max SMP | 1-Way (Uniprocessor) |
|
Power (idle) | 2.3 W |
Vcore | 0.3 V-1.52 V |
TDP | 17 W |
Tjunction | 0 °C – 100 °C |
Tstorage | -25 °C – 125 °C |
|
Package | FCBGA-1023 (BGA) |
Dimension | 31 mm x 24 mm |
Pitch | 0.65 mm |
Contacts | 1023 |
|
Core i3-2377M is a dual-core entry-level performance mobile x86 microprocessor introduced by Intel in 2012. Fabricated on a 32 nm process based on the Sandy Bridge microarchitecture, this processor operates at 1.5 GHz with a TDP of 17 Watts. The i3-2377M supports up to 16 GiB of dual-channel DDR3-1333 memory and incorporates Intel's HD Graphics 3000 integrated graphics operating at 350 MHz with a burst frequency of 1 GHz.
Cache
- Main article: Sandy Bridge § Cache
[Edit/Modify Cache Info]
|
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
|
L1$ | 128 KiB 131,072 B 0.125 MiB
| L1I$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 8-way set associative | |
---|
L1D$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 8-way set associative | write-back |
---|
|
---|
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB
| | | 2x256 KiB | 8-way set associative | write-back |
---|
|
---|
| L3$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB
| | | 2x1.5 MiB | 12-way set associative | write-back |
---|
|
---|
|
Memory controller
[Edit/Modify Memory Info]
|
Integrated Memory Controller
|
Max Type | DDR3-1333, DDR3-1066 |
---|
Supports ECC | No |
---|
Max Mem | 16 GiB |
---|
Controllers | 1 |
---|
Channels | 2 |
---|
Max Bandwidth | 19.87 GiB/s 20,346.88 MiB/s 21.335 GB/s 21,335.25 MB/s 0.0194 TiB/s 0.0213 TB/s
|
---|
Bandwidth |
Single 9.93 GiB/s Double 19.87 GiB/s
|
|
Expansions
Wireless
Wireless Communications |
Cellular |
4G | |
---|
Graphics
[Edit/Modify IGP Info]
|
Integrated Graphics Information
|
GPU | HD Graphics 3000 |
Designer | Intel | Device ID | 0x116 |
Execution Units | 12 | Max Displays | 2 |
|
Frequency | 350 MHz 0.35 GHz 350,000 KHz
| Burst Frequency | 1,000 MHz 1 GHz 1,000,000 KHz
|
---|
Output | DP, eDP, HDMI, SDVO, CRT |
---|
| Standards | DirectX | 10.1 |
---|
OpenGL | 3.1 | DP | 1.1 | eDP | 1.1 | HDMI | 1.4 |
|
---|
| Additional Features | |
|
[Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities
|
Codec |
Encode |
Decode
|
Profiles |
Levels |
Max Resolution |
Profiles |
Levels |
Max Resolution
|
MPEG-2 (H.262) |
✘ |
Main |
Main, High |
Up to 80 Mbps
|
MPEG-4 AVC (H.264) |
Main |
4.1 |
Up to 40 Mbps |
Main, High |
4.1 |
Up to 40 Mbps
|
VC-1 |
✘ |
Advanced, Main, Simple |
3, High, Simple |
Up to 40 Mbps
|
Features