| Edit Values |
| Cavium CN3630-600 EXP |
 |
|
| Designer | Cavium |
| Manufacturer | TSMC |
| Model Number | CN3630-600 EXP |
| Part Number | CN3630-600BG1521-EXP |
| Market | Networking |
| Introduction | August, 2005 (announced) August, 2005 (launched) |
|
| Family | OCTEON |
| Series | CN3600 |
| Frequency | 600 MHz |
|
| ISA | MIPS64 (MIPS) |
| Microarchitecture | cnMIPS |
| Core Name | cnMIPS |
| Process | 130 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 4 |
| Max Memory | 16 GiB |
|
| Max SMP | 1-Way (Uniprocessor) |
|
| Package | FCBGA-1521 (BGA) |
| Ball Count | 1521 |
| Interconnect | BGA-1521 |
|
The CN3630-600 EXP is a 64-bit quad-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 600 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
 |
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
|
| L1$ | 160 KiB 163,840 B 0.156 MiB
| | L1I$ | 128 KiB 131,072 B 0.125 MiB
| 4x32 KiB | 64-way set associative | |
|---|
| L1D$ | 32 KiB 32,768 B 0.0313 MiB
| 4x8 KiB | 64-way set associative | Write-through |
|---|
|
|---|
| | L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB
| | | | 1x512 KiB | 8-way set associative | |
|---|
|
|---|
|
Memory controller[edit]
[Edit/Modify Memory Info]
 |
Integrated Memory Controller
|
| Max Type | DDR2-800 |
|---|
| Supports ECC | Yes |
|---|
| Max Mem | 16 GiB |
|---|
| Controllers | 1 |
|---|
| Channels | 1 |
|---|
| Width | 64 bit |
|---|
| Max Bandwidth | 5.96 GiB/s 6,103.04 MiB/s 6.4 GB/s 6,399.501 MB/s 0.00582 TiB/s 0.0064 TB/s
|
|---|
| Bandwidth |
Single 5.96 GiB/s
|
|
Expansions[edit]
Networking[edit]
Hardware Accelerators[edit]
Block diagram[edit]
Datasheet[edit]