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AMD-K6-2/300ANZ-66 - AMD
Edit Values | |
K6-2/300ANZ-66 | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | K6-2/300ANZ-66 |
Part Number | AMD-K6-2/300ANZ-66 |
Market | Mobile |
Introduction | March 22, 1999 (announced) March 22, 1999 (launched) |
Shop | Amazon |
General Specs | |
Family | K6-2 |
Series | K6-2 Mobile |
Frequency | 299.99 MHz |
Bus type | FSB |
Bus speed | 66.66 MHz |
Bus rate | 66.66 MT/s |
Clock multiplier | 4.5 |
CPUID | 58C |
Microarchitecture | |
Microarchitecture | K6-2 |
Platform | Super 7 |
Core Name | Chomper Extended |
Core Family | 5 |
Core Model | 8 |
Core Stepping | 12 |
Process | 0.25 µm |
Transistors | 9,300,000 |
Technology | CMOS |
Die | 81 mm² |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Power dissipation | 10 W |
Vcore | 1.8 V ± 0.1 V |
VI/O | 3.3675 V ± 7% |
Tcase | 0 °C – 85 °C |
Tstorage | -65 °C – 150 °C |
K6-2/300ANZ-66 was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB operating at 66 MHz.
Contents
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
Documents
DataSheet
- Mobile AMD-K6-2 Processor Data Sheet; Publication #21896 Revision E/0, May 2000
Facts about "AMD-K6-2/300ANZ-66 - AMD"
l1d$ description | 2-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |