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PEZY-SC2 - PEZY
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Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor.

PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate2,000 MHz
Width1,024 bit
Channels4
Max Bandwidth1.863 TiB/s
1,907.712 GiB/s
1,953,497.088 MiB/s
2,048.39 GB/s
2,048,390.163 MB/s
2.048 TB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes32
Configsx16, x8, x4
UART
GP I/OYes
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Facts about "PEZY-SC2 - PEZY"
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PEZY-SC2 - PEZY#io +
has ecc memory supporttrue + and false +
max memory bandwidth1,907.712 GiB/s (1,953,497.088 MiB/s, 2,048.39 GB/s, 2,048,390.163 MB/s, 1.863 TiB/s, 2.048 TB/s) +
max memory channels4 +
max pcie lanes32 +
supported memory typeDDR4-2666 +