Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor.

PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Memory controller

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	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Controllers 8 Channels 8 Max Bandwidth 158.95 GiB/s 162,764.8 MiB/s 170.671 GB/s 170,671.263 MB/s 0.155 TiB/s 0.171 TB/s Bandwidth Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s Octa 158.95 GiB/s

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Memory Wide I/O Rate 2,000 MHz Width 1,024 bit Channels 4 Max Bandwidth 1.863 TiB/s 1,907.712 GiB/s 1,953,497.088 MiB/s 2,048.39 GB/s 2,048,390.163 MB/s 2.048 TB/s

Expansions

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	Expansion Options
	PCIe Revision 3.0 Max Lanes 32 Configs x16, x8, x4 UART GP I/O Yes