Template:mpu QorIQ P1012 is a 32-bit dual-core embedded POWER microprocessor introduced by Freescale in late 2009. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1,200 MHz and supports 32-bit DDR3-800 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 8-way set associative Write-through

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-800 Supports ECC Yes Controllers 1 Channels 1 Width 32 bit Max Bandwidth 2.98 GiB/s 3,051.52 MiB/s 3.2 GB/s 3,199.751 MB/s 0.00291 TiB/s 0.0032 TB/s Bandwidth Single 2.98 GiB/s

Expansions

• 3x 10/100/1000 Eithernet with 2x SGMII
• 2x PCIe 1.0a controllers with 4 SerDes
• 2x USB 2.0
• SD/MMC
• SPI
• 2x I2C
• UART
• SEC 3.3 Security Acceleration

Block Diagram

Documents

• P1012/P1021 Product Brief