Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Cache

Main article: ARM9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 32 KiB 32,768 B 0.0313 MiB L1I$ 16 KiB 16,384 B 0.0156 MiB 1x16 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 1x16 KiB 4-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR Controllers 1 Channels 1 Width 16 bit, 32 bit

Documents

• K3V1 Product Brief