Cache

Main article: Sandy Bridge § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative write-back L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     4x256 KiB 8-way set associative write-back L3$ 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB     4x1.5 MiB 12-way set associative write-back

Memory controller

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	Integrated Memory Controller
	Max Type DDR3-1600, DDR3-1333, DDR3-1066 Supports ECC No Max Mem 16 GiB Controllers 1 Channels 2 Max Bandwidth 23.84 GiB/s 24,412.16 MiB/s 25.598 GB/s 25,598.005 MB/s 0.0233 TiB/s 0.0256 TB/s Bandwidth Single 11.92 GiB/s Double 23.84 GiB/s

Expansions

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	Expansion Options
PCIe Revision: 2.0 Max Lanes: 20 Configuration: 1x16+1x4, 2x8+1x4, 1x8+3x4

Features

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	Supported x86 Extensions & Processor Features