Template:mpu
R-Car M1A is a mid-range performance embedded dual-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1A features a single Cortex-A9 core and an additional SH-4A core, both operating at 800 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.
Cache
- Main article: Cortex-A9 § Cache
[Edit/Modify Cache Info]
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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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L1$ | 128 KiB 131,072 B 0.125 MiB
| L1I$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 4-way set associative | |
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L1D$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 4-way set associative | |
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Memory controller
[Edit/Modify Memory Info]
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Integrated Memory Controller
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Max Type | DDR2-800 |
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Supports ECC | No |
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Max Mem | 1 GiB |
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Controllers | 1 |
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Channels | 2 |
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Width | 32 bit |
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Max Bandwidth | 7.95 GiB/s 8,140.8 MiB/s 8.536 GB/s 8,536.248 MB/s 0.00776 TiB/s 0.00854 TB/s
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Bandwidth |
Single 3.97 GiB/s Double 7.95 GiB/s
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Expansions
- MLB (MOST150) 6-Pin I/F
- 2 x CAN 32 Message Buffers
- MMC
- 3 x SD
Graphics
- 20MPoly/s; 1000MPix/s; 3.2GFlops/s
[Edit/Modify IGP Info]
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Integrated Graphics Information
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GPU | PowerVR SGX540 |
Designer | Imagination Technologies |
Execution Units | 2 | Max Displays | 2 |
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Frequency | 200 MHz 0.2 GHz 200,000 KHz
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Features
[Edit/Modify Supported Features]
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Thumb-2 | Thumb-2 Extension |
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ThumbEE | Thumb Execution Environment Extension |
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VFPv3 | Vector Floating Point (VFP) v3 Extension |
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NEON | Advanced SIMD extension |
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Jazelle | Direct Bytecode eXecution |
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