Template:mpu Celeron 3955U is a 64-bit dual-core budget x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2 GHz. The 3955U has a TDP of 15 W with a configurable-down TDP of 10 W. This chip incorporates the HD Graphics 510 GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     2x1 MiB   write-back

Graphics

Integrated Graphic Information
GPU	Intel HD Graphics 510
Displays	3
Frequency	300 MHz 0.3 GHz 300,000 KHz
Max frequency	900 MHz 0.9 GHz 900,000 KHz
Max memory	1700 MiB 1,740,800 KiB 1,782,579,200 B 1.66 GiB
Output	DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX	12
OpenGL	4.4
Max HDMI Res	4096x2304 @24 Hz
Max DP Res	4096x2304 @60 Hz
Max eDP Res	4096x2304 @60 Hz

Memory controller

Integrated Memory Controller
Type	DDR4-1866, DDR4-2133, LPDDR3-1600, LPDDR3-1866
Controllers	1
Channels	2
Max bandwidth	34,100 MB/s
Max memory	32,768 MB