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From WikiChip
Alpha 21164 - Microarchitectures - DEC
< dec
Edit Values | |
Alpha 21164 µarch | |
General Info | |
Arch Type | CPU |
Designer | DEC |
Manufacturer | DEC |
Introduction | January, 1995 |
Process | 0.5 µm |
Core Configs | 1 |
Pipeline | |
Type | Superscalar |
OoOE | No |
Speculative | Yes |
Reg Renaming | No |
Stages | 7-9 |
Decode | 4-way |
Instructions | |
ISA | Alpha |
Cache | |
L1I Cache | 8 KiB/core direct-mapped |
L1D Cache | 8 KiB/core direct-mapped |
L2 Cache | 96 KiB/core 3-way set associative |
Succession | |
Alpha 21164 was an Alpha microarchitecture designed by DEC and introduced in 1995 as a successor to the Alpha 21064 architecture.
Retrieved from "https://en.wikichip.org/w/index.php?title=dec/microarchitectures/alpha_21164&oldid=44607"
Facts about "Alpha 21164 - Microarchitectures - DEC"
codename | Alpha 21164 + |
core count | 1 + |
designer | DEC + |
first launched | January 1995 + |
full page name | dec/microarchitectures/alpha 21164 + |
instance of | microarchitecture + |
instruction set architecture | Alpha + |
manufacturer | DEC + and Samsung + |
microarchitecture type | CPU + |
name | Alpha 21164 + |
pipeline stages (max) | 12 + |
pipeline stages (min) | 7 + |
process | 500 nm (0.5 μm, 5.0e-4 mm) + |