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DATA BUS I/O | D0 | 01 | 16 | CM-RAM0 | X | |||
D1 | 02 | 15 | CM-RAM1 | X | ||||
D2 | 03 | 14 | CM-RAM2 | X | ||||
D3 | 04 | 13 | CM-RAM3 | X | ||||
Vss | 05 | 12 | Vdd | X | ||||
CLOCK PHASE 1/2 | Ø1 | 06 | 11 | CM-ROM | X | |||
Ø2 | 07 | 10 | TEST | X | ||||
SYNC | 08 | 09 | RESET | X | ||||
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
Cache Info Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. [Edit Values]The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes. | ||||||||||||
L1$ | 128 KiB |
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L2$ | 128 KiB |
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L3$ | 128 KiB |
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L4$ | 128 KiB |
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Off-package cache support | ||||||||||||
Mobo | 512 KiB |
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Contents
wireless test
mpu
AMD-X5-133ADW | |
General Info | |
Designer | AMD |
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Manufacturer | AMD |
Model Number | AMD-X5-133ADW |
Part Number | AMD-X5-133ADW, AMD-X5-133ADW, AMD-X5-133ADW |
Market | Desktop |
Market | Desktop |