Template:mpu Ryzen 5 1600X is a 64-bit hexa-core mid-range performance x86 desktop microprocessor set to be introduced by AMD in early 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 1600X operates at a base frequency of 3.6 GHz with a TDP of 95 W and a Boost frequency of 4 GHz. This model is better suited for overclocking (as opposed to the various other Ryzen 5 models). This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 576 KiB 589,824 B 0.563 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 6x64 KiB 4-way set associative   L1D$ 192 KiB 196,608 B 0.188 MiB 6x32 KiB 8-way set associative write-back L2$ 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB     6x512 KiB 8-way set associative write-back L3$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     2x8 MiB 16-way set associative