Cavium OCTEON Plus
Developer	Cavium
Manufacturer	TSMC
Type	System on chips
Introduction	October 9, 2006 (announced) February, 2007 (launch)
Architecture	MIPS64 R2 network SoCs
ISA	MIPS64
µarch	cnMIPS
Word size	64 bit 8 octets 16 nibbles
Process	130 nm 0.13 μm 1.3e-4 mm
Technology	CMOS
Clock	600 MHz-1,000 MHz
Package	FCBGA-1521
Socket	BGA-1521
Succession
←	→
OCTEON	OCTEON II

OCTEON Plus was a family of 64-bit multi-core MIPS microprocessors designed by Cavium and introduced in 2007. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the OCTEON family offering double the cache, double the clock speeds, and double the number of various acceleration units.

Overview

The OCTEON Plus family was announced in late 2006 as a successor to the original OCTEON family. As with the previous family, the OCTEON Plus is also based on the cnMIPS microarchitecture. These new processors operate at twice the previous clock speeds and introduced a number of incremental improvements such as a larger cache.

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