Semiconductor & Computer Engineering
From WikiChip
OCTEON Plus - Cavium
| Cavium OCTEON Plus | |
| Developer | Cavium |
| Manufacturer | TSMC |
| Type | System on chips |
| Introduction | October 9, 2006 (announced) February, 2007 (launch) |
| Architecture | MIPS64 R2 network SoCs |
| ISA | MIPS64 |
| µarch | cnMIPS |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 130 nm 0.13 μm
1.3e-4 mm |
| Technology | CMOS |
| Clock | 600 MHz-1,000 MHz |
| Package | FCBGA-1521 |
| Socket | BGA-1521 |
| Succession | |
| ← | → |
| OCTEON | OCTEON II |
OCTEON Plus was a family of 64-bit multi-core MIPS microprocessors designed by Cavium and introduced in 2007. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the OCTEON family offering double the cache, double the clock speeds, and double the number of various acceleration units.
Facts about "OCTEON Plus - Cavium"
| designer | Cavium + |
| first announced | October 9, 2006 + |
| first launched | February 2007 + |
| full page name | cavium/octeon plus + |
| instance of | system on a chip family + |
| instruction set architecture | MIPS64 + |
| main designer | Cavium + |
| manufacturer | TSMC + |
| microarchitecture | cnMIPS + |
| name | Cavium OCTEON Plus + |
| package | FCBGA-1521 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| socket | BGA-1521 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |