Template:mpu
The CN3860-500 EXP is a 64-bit hexadeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
|
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
|
L1$ | 640 KiB 655,360 B 0.625 MiB
| L1I$ | 512 KiB 524,288 B 0.5 MiB
| 16x32 KiB | 64-way set associative | |
---|
L1D$ | 128 KiB 131,072 B 0.125 MiB
| 16x8 KiB | 64-way set associative | Write-through |
---|
|
---|
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB
| | | 1x1 MiB | 8-way set associative | |
---|
|
---|
|
Memory controller
[Edit/Modify Memory Info]
|
Integrated Memory Controller
|
Max Type | DDR2-800 |
---|
Supports ECC | Yes |
---|
Max Mem | 16 GiB |
---|
Controllers | 1 |
---|
Channels | 1 |
---|
Width | 128 bit |
---|
Max Bandwidth | 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s
|
---|
Bandwidth |
Single 11.92 GiB/s
|
|
Expansions
Networking
Hardware Accelerators
Block diagram
Datasheet