Template:mpu
The CN3630-600 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 600 MHz and dissipates 30 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
![hierarchy icon.svg](/w/images/thumb/e/e4/hierarchy_icon.svg/75px-hierarchy_icon.svg.png) |
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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L1$ | 160 KiB 163,840 B 0.156 MiB
| L1I$ | 128 KiB 131,072 B 0.125 MiB
| 4x32 KiB | 64-way set associative | |
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L1D$ | 32 KiB 32,768 B 0.0313 MiB
| 4x8 KiB | 64-way set associative | Write-through |
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| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB
| | | 1x512 KiB | 8-way set associative | |
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Memory controller
[Edit/Modify Memory Info]
![ram icons.svg](/w/images/thumb/a/af/ram_icons.svg/75px-ram_icons.svg.png) |
Integrated Memory Controller
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Max Type | DDR2-800 |
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Supports ECC | Yes |
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Max Mem | 16 GiB |
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Controllers | 1 |
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Channels | 1 |
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Width | 64 bit |
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Max Bandwidth | 5.96 GiB/s 6,103.04 MiB/s 6.4 GB/s 6,399.501 MB/s 0.00582 TiB/s 0.0064 TB/s
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Bandwidth |
Single 5.96 GiB/s
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Expansions
Networking
Hardware Accelerators
[Edit/Modify Accelerators Info]
![hardware accel icon.svg](/w/images/thumb/b/b0/hardware_accel_icon.svg/75px-hardware_accel_icon.svg.png) |
Hardware Accelerators
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Encryption | Hardware Implementation | Yes |
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Types | DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH |
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RegEx | RegEx | Yes |
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Features | 16 Engines |
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Compression | Compression | Yes |
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Decompression | Yes |
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Block diagram
Datasheet