Semiconductor & Computer Engineering
From WikiChip
CN3120-500 CP - Cavium
Facts about "CN3120-500 CP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3120-500 CP - Cavium#package + |
| base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
| core count | 2 + |
| core name | cnMIPS + |
| designer | Cavium + |
| family | OCTEON + |
| first announced | January 30, 2006 + |
| first launched | May 1, 2006 + |
| full page name | cavium/octeon/cn3120-500bg868-cp + |
| has ecc memory support | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
| ldate | May 1, 2006 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
| max memory channels | 1 + |
| microarchitecture | cnMIPS + |
| model number | CN3120-500 CP + |
| name | Cavium CN3120-500 CP + |
| package | HSBGA-868 + |
| part number | CN3120-500BG868-CP + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| series | CN3100 + |
| smp max ways | 1 + |
| supported memory type | DDR2-667 + |
| technology | CMOS + |
| thread count | 2 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
