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From WikiChip
SC2A11 - Socionext
Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.
Facts about "SC2A11 - Socionext"
| l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |