Template:mpu Xeon E7-4820 is a 64-bit octa-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 512 KiB 524,288 B 0.5 MiB L1I$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 4-way set associative write-back L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative write-back L2$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     8x256 KiB 8-way set associative write-back L3$ 18 MiB 18,432 KiB 18,874,368 B 0.0176 GiB     8x2.25 MiB 16-way set associative write-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR3-800, DDR3-978, DDR3-1066
Controllers	1
Channels	4
ECC Support	Yes
Max memory	2048 GB