Template:mpu Core i7-640UM is a 64-bit dual-core x86-64 mobile microprocessor designed by Intel and introduced in early 2010. This chip is a first-generation Core i7 processor based on the Westmere microarchitecture and is manufactured on a 32 nm process. This processor operated at a based frequency of 1.2 GHz with a turbo frequency of 2.27 GHz and a TDP of 18 W. This MPU came with a HD Graphics (Ironlake) IGP operating at 166 MHz with a max burst frequency of 500 MHz.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative write-back L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 8-way set associative write-back L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     2x2 MiB 16-way set associative write-back

Memory controller

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	Integrated Memory Controller
	Max Type DDR3-800 Supports ECC No Max Mem 8 GiB Controllers 1 Channels 2 Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 5.96 GiB/s Double 11.92 GiB/s Physical Address (PAE) 36 bit

Expansions

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	Expansion Options
	PCIe Revision 2.0 Max Lanes 16 Configs 1x16