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Piton - Princeton
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Template:mpu Piton is a 64-bit many-core microprocessor developed by Princeton's Parallel Computing Group and announced in August of 2016. The MPPA chip contains 25 modified OpenSPARC T1 cores (an implementation of SPARC V9). The chip, which was manufactured on IBM's 32 nm SOI process, operates at 1 GHz. The chip was presented On August 32 2016 at the Hot Chips 28.

Architecture

The chip is designed as a massively parallel processor array, with 25 cores ("tiles") arranged as a grid 5 by 5. Each core is a modified OpenSPARC T1 which implements SPARC V9 capable of booting a standard OS. Piton implements a 64-bit network on chip (NoC) interconnect made of 3 physical networks operating at 1 cycle/hop latency.

piton layout.svg

Tiles

Piton is made of an array of tiles in a grid of 5x5. Each tile is composed of a modified OpenSPARC T1 core (+L1$), an L1.5 cache, L2 cache, a floating-point unit (FPU), a CPU Cache-Crossbar (CCX) arbiter, and three network on chip (NoC) routers.

Cache

Pitons uses a distributed write-back L2$ model that implements a directory-based MESI protocol - adhering to OpenSPARC's total store order (TSO) model. Each tile contains 64 KB slice of the L2 cache and an attached cache directory. The L2 cache is inclusive of both the L1.5$ and the L1$. Note that the L1.5 is called as such because the OpenSPARC T1 core already implements an 8 KB L1d$ and 16 KB L1i$ which are tightly coupled with the pipeline and was thus only modified to work in a scaleable multi-core environment. The L1.5$ acts as a middleman between the OpenSPARC T1's crossbar protocol and the Piton's NoC. It relays requests and replies to and from the core through CCX.

Cache Info [Edit Values]
L1D$ 200 KB
"KB" is not declared as a valid unit of measurement for this property.
 		25x8 KB 4-way set associative (write-back, per tile)
L2$ 1.6 MB
"MB" is not declared as a valid unit of measurement for this property.
 		25x64 KB 4-way set associative (per tile)

Network On-chip (NoC)

Piton implements 3 physical networks on chip (NoC) that provide all the communication between the tiles, deliver I/O and memory traffic, and pass inter-core interrupts. Piton implements 3 physical neworks - each consisting of two 64-bit uni-directional links (one in each direction). Packets routing implements dimension-order routing. Each packet reserves 29 bits for core address, allowing a theoretical network size 500 million core. The three NoCs have descending priorities - i.e. NoC3 has the highest priority, followed by NoC2, followed by NoC1 with the lowest priority.

Documents

External links

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Facts about "Piton - Princeton"
RDF feed
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus rate2,800 MT/s (2.8 GT/s, 2,800,000 kT/s) +
bus speed350 MHz (0.35 GHz, 350,000 kHz) +
clock multiplier2.85 +
core count25 +
core voltage0.9 V (9 dV, 90 cV, 900 mV) +
designerPrinceton +
die area36 mm² (0.0558 in², 0.36 cm², 36,000,000 µm²) +
die length6 mm (0.6 cm, 0.236 in, 6,000 µm) +
die width6 mm (0.6 cm, 0.236 in, 6,000 µm) +
first announcedAugust 23, 2016 +
full page nameprinceton/piton +
instance ofmicroprocessor +
l1d$ description4-way set associative +
l1d$ size200 KiB (204,800 B, 0.195 MiB) +
l2$ description4-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
ldateAugust 23, 2016 +
main imageFile:Princeton piton.png +
main image captionPiton face +
manufacturerIBM +
market segmentServer +
max cpu count20,000 +
namePiton +
process32 nm (0.032 μm, 3.2e-5 mm) +
smp max ways20,000 +
technologyCMOS +
thread count50 +
transistor count460,000,000 +
word size64 bit (8 octets, 16 nibbles) +