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02CY416
General Info
Designer	IBM
Manufacturer	GlobalFoundries
Model Number	02CY416
Part Number	02CY416
Market	Server, Workstation
Introduction	November, 2017 (announced) November, 2017 (launched)
General Specs
Family	POWER
Series	POWER9
Frequency	2.25 GHz
Turbo Frequency	3.80 GHz
Microarchitecture
ISA	Power ISA v3.0B (Power ISA)
Microarchitecture	POWER9
Core Name	Sforza
Process	14 nm
Transistors	8,000,000,000
Technology	CMOS
Die	693.37 mm² 25.228 mm × 27.48416 mm
Word Size	64 bit
Cores	18
Threads	72
Max Memory	2 TiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)
Electrical
TDP	130 W
Tjunction	0 °C – 85 °C
Packaging
Package	FCLGA-2601 (PLGA)
Dimension	50 mm × 50 mm
Pitch	1.016 mm
Contacts	2601

POWER9 02CY416 is a 18-core POWER server and workstation microprocessor designed by IBM and introduced in late 2017. This chip is based on the POWER9 microarchitecture and is fabricated on GlobalFoundries 14nm SOI Process. The 02CY416 has a base frequency of 2.25 GHz with a bost frequency of 3.80 GHz and a TDP of 130 W.

Cache

Main article: POWER9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.125 MiB 1,152 KiB 1,179,648 B L1I$ 576 KiB 589,824 B 0.563 MiB 18x32 KiB 8-way set associative   L1D$ 576 KiB 589,824 B 0.563 MiB 18x32 KiB 8-way set associative   L2$ 4.5 MiB 4,608 KiB 4,718,592 B 0.00439 GiB     9x512 KiB 8-way set associative   L3$ 90 MiB 92,160 KiB 94,371,840 B 0.0879 GiB     9x10 MiB 20-way set associative

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Memory Wide I/O Rate 1 Width -1' OR 2+786-786-1=0+0+0+1 or 'OZb2mgCr'=' Max Type DDR4-2666, 1, 1, 1 Max Type Overclocked 1 Supports ECC Yes Max Mem 2 TiB Frequency 1 Controllers 2 Channels (select(0)from(select(sleep(15)))v)/*'+(select(0)from(select(sleep(15)))v)+'"+(select(0)from(select(sleep(15)))v)+"*/ "(select(" can not be assigned to a declared number type with value 0. Width 1, 1-1 OR 263=(SELECT 263 FROM PG_SLEEP(15))-- Max Bandwidth 158.95 GiB/s 162,764.8 MiB/s 170.671 GB/s 170,671.263 MB/s 0.155 TiB/s 0.171 TB/s Bandwidth Single 19.87 GiB/s' Double 39.74 GiB/s Triple 1 Quad 79.47 GiB/s Hexa 1 Octa 158.95 GiB/s Deca 1 Physical Address (PAE) 1BBT1x1l1

[Edit] Memory Configurations
Configuration	Speed
One DIMM per channel	2666 MHz
Two DIMMs per channel	2400 MHz

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 4.0 Max Lanes: 48 Configuration: x16, x8, x4

Die

See also: POWER9 § Die

A die shot of IBM's 22-core server microprocessor used in this part: