• arm holdings/microarchitectures/cortex-a77
  [[File:arm deimos roadmap.png|right|thumb|Arm client roadmap with Deimos.]] :[[File:cortex-a77 soc block diagram.svg|450px]]
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  [[File:arm deimos roadmap.png|right|thumb|Arm client roadmap with Hercules.]] *** Register renaming unit
  21 KB (3,067 words) - 09:25, 31 March 2022
• arm/armv8
  ...nk between the two modes of execution and it is not possible to reduce the register width going from one exception to a higher exception level. Those restricti :[[File:armv8 32-64 movement.svg|600px]]
  6 KB (817 words) - 06:37, 24 April 2020
• arm/a64
  ...e [[program counter]] is no longer treated as a normal directly accessible register. ...ones but are instead mapped one-to-one to the low-order bits of the bigger register.
  3 KB (446 words) - 01:03, 19 January 2022
• intel/configurable spatial accelerator
  [[File:csa overview block.svg|thumb|right|Overview]] [[File:csa overview full chip.svg|400px]]
  14 KB (2,130 words) - 20:19, 2 October 2018
• sifive/microarchitectures/7 series
  :[[File:sifive 7 series cluster.svg|500px]] :[[File:sifive 7 series block diagram.svg|600px]]
  4 KB (625 words) - 09:16, 28 November 2018
• intel/dl boost
  ...Matrix Extension}} (AMX) - an extension that introduces a matrix register file and matrix operations. AMX was first introduced with {{intel|Sapphire Rapid
  2 KB (324 words) - 21:39, 30 June 2020
• nec/microarchitectures/sx-aurora
  :[[File:sx-aurora block diagram.svg|600px]] :[[File:sx-aurora vector core block diagram.svg|700px]]
  16 KB (2,497 words) - 13:30, 15 May 2020
• intel/microarchitectures/sunny cove
  [[File:sunny cove roadmap.png|thumb|right|200px|Intel Core roadmap]] :[[File:14nm improv 10 delays.svg|500px]]
  34 KB (5,187 words) - 06:27, 17 February 2023
• ibm/microarchitectures/z15
  **** Larger integer physical register files (???, up from 120 entries) **** Larger vector physical register files (???, up from 127 entries)
  7 KB (912 words) - 16:31, 7 May 2020
• umich/microarchitectures/vanilla-5
  ...ipelined|5-stage]] design. Each core incorporates a 32-entry, 32b register file which is implemented using two 1R1W latch-based [[sram|memory]] as well as :[[File:vanilla-5 core.png|600px]]
  3 KB (393 words) - 18:35, 20 January 2020
• centaur/microarchitectures/cha
  :[[File:cha soc block diagram.svg|450px]] :[[File:cns block diagram.svg|750px]]
  24 KB (3,792 words) - 04:37, 30 September 2022
• arm holdings/microarchitectures/mlp
  :[[File:mlp block diagram.svg|500px]] :[[File:mlp compute engine block diagram.svg|550px]]
  9 KB (1,379 words) - 22:35, 6 February 2020
• amd/List of AMD publications
  |18448||D||[[:File:CPU Thermal Management (Am486, Am5x86, K5) (August 1995).pdf|CPU Thermal Ma |18495||D||[[:File:Phase Lock Loop (PLL) Clock Control (Am486, Am5x86, K5) (August 1995).pdf|P
  181 KB (24,894 words) - 16:24, 12 June 2024
• arm/helium
  ...ter file. This was done in order to reduce pressure on the vector register file. :[[File:helium vector reg file alias.svg|500px]]
  6 KB (986 words) - 19:09, 2 October 2020
• x86/amx
  ...'AMX''') is an [[x86]] {{x86|extension}} that introduces a matrix register file and new instructions for operating on matrices. [[File:amx architecture.svg|thumb|right|AMX Architecture]]
  5 KB (743 words) - 21:40, 30 June 2020
• arm holdings/microarchitectures/cortex-a510
  :[[File:cortex-a510 block diagram.svg|1000px]] [[File:cortex-a510-complex-overview.svg|right|200px]]
  15 KB (2,282 words) - 11:20, 10 January 2023
• alchemy/microarchitectures/au1
  ...{{abbr|GPR}}s and CP0 registers are preserved in both modes, the CP0 Count register increments at an unpredictable rate (an unaffected {{abbr|RTC}} is integrat ...cite techdoc|title=AMD Alchemy™ Au1000™ Processor Specification Update|file=AMD-27348-E Au1000 Spec Update.pdf|publ=AMD|pid=27348|rev=E|date=2005-06}}.
  13 KB (2,114 words) - 16:00, 17 April 2022
• alchemy/alchemy
  Au1000 processors identify with {{mips|PRId register|PRId}} 0x00030101 (Au1 rev. 1, stepping DA) and 0x00030201 to 0x00030204 (A [[:File:Au1300 pinmap.svg|Au13xx Pin Map]]
  31 KB (4,972 words) - 03:09, 20 March 2022

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