• intel/cores/skylake h
  | image = skylake h (front).png | image size = 250px
  5 KB (630 words) - 02:08, 16 January 2019
• dec/alpha
  | image = | no image = Yes
  3 KB (388 words) - 06:17, 18 June 2017
• intel/cores/skylake u
  |image=skylake u (front; iris).png |image size=250px
  5 KB (743 words) - 08:07, 21 August 2017
• intel/microarchitectures/skylake (server)
  Unlike mainstream Skylake models, all Skylake server configuration models are fabricated on Intel's [[14 nm process#Intel|enhanced 14+ nm process]] w ...ke (client)}} architecture. Unlike client models, Skylake servers and HEDT models will still incorporate the fully integrated voltage regulator (FIVR) on-die
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/cores/coffee lake s
  |image=coffee lake s (front).png |image 2=coffee lake s (back).png
  4 KB (546 words) - 08:18, 1 January 2020
• intel/cores/coffee lake h
  |image=coffee lake h (front).png All Coffee Lake H processors have the following:
  5 KB (648 words) - 17:43, 6 December 2018
• intel/cores/sandy bridge m
  |no image=Yes ...}. Those processors cover the entire mobile segment from budget processors all the way to high-end performance.
  3 KB (489 words) - 15:57, 4 September 2017
• intel/cores/denverton
  |image=denverton (front).png All Denverton models have the following features:
  7 KB (950 words) - 06:47, 25 April 2020
• intel/celeron/807ue
  |no image=Yes ...ed graphics]] operating at 350 MHz with a burst frequency of 800 MHz. This processor supports 4 GiB of single-channel DDR3-1333 ECC memory.
  5 KB (662 words) - 19:19, 17 March 2018
• intel/cores/kaby lake r
  |no image=Yes |image=kaby lake r (front).png
  5 KB (751 words) - 09:52, 11 February 2019
• apple/ax/a11
  |no image=No ...nce controller", this restriction has been removed. The system can now use all six cores at once and is said to offer up to 70% performance improvement in
  4 KB (661 words) - 23:51, 3 January 2021
• microsoft/scorpio engine
  |image=scorpio engine (front).png ...It's worth pointing out that [[AMD]] has not commercialized a 16 nm Jaguar processor outside of this chip.
  15 KB (2,390 words) - 02:54, 17 May 2023
• amd/microarchitectures/zen+
  ...for many mainboards. But drivers must be integrated into the installation image or installed first before switching to a Zen-based system. Otherwise suppor *** Summit Ridge, Naples: 8 MiB/CCX, shared across all cores.
  11 KB (1,613 words) - 08:39, 3 March 2024
• intel/pentium gold
  | image = intel pentium gold logo (2017).png | no image =
  10 KB (1,338 words) - 11:10, 8 April 2018
• nxp/qoriq
  | image = | no image = Yes
  6 KB (795 words) - 20:23, 31 October 2017
• amd/cores/raven ridge
  |no image=Yes All Raven Ridge processors have the following:
  3 KB (418 words) - 13:58, 17 March 2023
• pezy/pezy-scx
  | image = | no image = Yes
  6 KB (838 words) - 09:33, 9 May 2019
• neural processor
  {{title|Neural Processor}} ...te [[machine learning]] algorithms, typically by operating on [[predictive models]] such as [[artificial neural network]]s (ANNs) or [[random forest]]s (RFs)
  5 KB (640 words) - 16:27, 26 September 2023
• amd/cores/picasso
  |no image=Yes All Picasso processors have the following:
  4 KB (598 words) - 14:04, 17 March 2023
• intel/xeon phi
  | image = xeon phi (2015).png {{comp table header|main|9:Main processor}}
  4 KB (444 words) - 01:38, 19 December 2017

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