• accelerator
  ...mponent attached to a system, but may also be integrated directly into the processor, sometimes in the form of an [[ISA]] extension. ...Whereas a co-processor is typically connected to the internals of the host processor, which then passes it instructions to execute, a generic accelerator is typ
  4 KB (539 words) - 19:47, 2 April 2019
• intel/etann
  ...analog synapses. The ETANN is also the first commercial [[analog]] neural processor and is considered to be the first successful commercial neural network chip ...volatile EEPROM analog synaptic weight array and a 64-element analog input vector. The chip was reported the calculations to reach 2000 MCPs (million connect
  4 KB (568 words) - 17:12, 11 February 2018
• intel/microarchitectures/cascade lake
  * {{x86|avx512vnni|<code>AVX-512 VNNI</code>}} - AVX-512 Vector Neural Network Instructions ...uses a single heat spreader designed to cover the entire TDP range for all processor models. In total, each package exposes 12 channel DDR4 supporting rates of
  32 KB (4,535 words) - 05:44, 9 October 2022
• amd/cores/picasso
  {{comp table header|main|9:Processor}} {{comp table header|main|7:Main Processor|2:Integrated Graphics}}
  4 KB (598 words) - 14:04, 17 March 2023
• intel/microarchitectures/knights mill
  * {{x86|AVX5124VNNI|<code>AVX5124VNNI</code>}} - AVX-512 Vector Neural Network * {{x86|AVX512VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} - AVX-512 Vector Population Count Doubleword and Quadword
  3 KB (388 words) - 02:47, 20 May 2019
• nervana/microarchitectures/spring crest
  ...''' ('''SCR''') is the successor to {{\\|Lake Crest}}, a training [[neural processor]] microarchitecture designed by [[Intel Nervana]] for the data center and w ...successor to {{\\|Lake Crest}}, Intel Nervana's first commercial [[neural processor]] that made it to mass production. The chip itself is designed for training
  11 KB (1,646 words) - 13:35, 26 April 2020
• nvidia/tegra/xavier
  Xavier is an autonomous machine processor designed by [[Nvidia]] and introduced at CES 2018. Silicon came back in the ...ht-core CPU cluster, GPU with additional inference optimizations, [[neural processor|deep learning accelerator]], vision accelerator, and a set of multimedia ac
  8 KB (1,263 words) - 03:08, 9 December 2019
• samsung/microarchitectures/m1
  ...cheduler which consists of 32 entries. There is a 96-entry floating point (vector) [[physical register file]] (roughly 35-36 architected). There are two pipe {{comp table header|main|6:Main processor|2:Integrated Graphics}}
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  ****** crypto EU, simple vector EU, vector shuffle/shift/mul, new FP store, new FP conversion ..., the FP FRP has also doubled in capacity with a 192-entry floating point (vector) [[physical register file]] (roughly 35-36 architected). There are three pi
  20 KB (3,149 words) - 10:44, 15 February 2020
• greenwaves/gap8
  ...e]] RISC-V cores capable of running at up to 250 MHz along with a [[neural processor]] designed to accelerate [[convolutional neural network]]s (CNN). The GAP8 ...added for operating on [[Convolutional Neural Networks]] (CNNs), [[Support Vector Machines]] (SVMs), [[Bayesian]], Boosting, Visual Location, [[Fast Fourier
  6 KB (981 words) - 14:11, 28 February 2018
• amd/cores/renoir
  * "''U''" suffix indicates a standard (15 W) mobile processor * "''H''" suffix indicates a high-power (45 W) mobile processor
  5 KB (681 words) - 14:07, 17 March 2023
• movidius/microarchitectures/shave v2.0
  '''Streaming Hybrid Architecture Vector Engine v2.0''' ('''SHAVE v2.0''') is an accelerator microarchitecture desig * 128-bit vector arithmetic
  12 KB (1,749 words) - 19:05, 20 January 2021
• intel/cores/cascade lake sp
  ...{{intel|Xeon Silver}}, {{intel|Xeon Gold}}, and {{intel|Xeon Platinum}} [[processor families]]. {{comp table header|main|8:Main Processor|1:Cache|2:Memory}}
  9 KB (1,291 words) - 13:48, 27 February 2020
• qualcomm/vision intelligence/qcs603
  ...eleration, this chip incorporates an Hexagon 685 vector processor with two vector extensions and an {{qualcomm|Adreno 615}} GPU. * {{qualcomm|Hexagon 685}} Vector Processor
  3 KB (302 words) - 22:05, 12 April 2018
• qualcomm/vision intelligence/qcs605
  ...eleration, this chip incorporates an Hexagon 685 vector processor with two vector extensions and an {{qualcomm|Adreno 615}} GPU. * {{qualcomm|Hexagon 685}} Vector Processor
  3 KB (302 words) - 22:05, 12 April 2018
• qualcomm/snapdragon 700/710
  ...{qualcomm|Hexagon}} {{qualcomm|Hexagon 685|685}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 250|250}} image sensor processor
  5 KB (610 words) - 11:04, 5 July 2020
• qualcomm/snapdragon 700/730
  ...{qualcomm|Hexagon}} {{qualcomm|Hexagon 688|688}} DSP with a Hexagon Vector Processor. * Qualcomm {{qualcomm|Spectra}} {{qualcomm|Spectra 350|350}} image sensor processor
  4 KB (535 words) - 07:01, 10 September 2021
• samsung/microarchitectures/m4
  ...quare root unit, a second vector multiplication unit, and a new horizontal vector arithmetic unit. {{comp table header|main|5:Main processor|2:Integrated Graphics|{{abbr|TDP}}|2:TDP down|2:TDP up}}
  5 KB (680 words) - 14:43, 16 March 2023
• intel/cores/ice lake y
  {{comp table header|main|8:Main processor|3:Integrated Graphics}} |theme=vector
  5 KB (731 words) - 19:08, 26 February 2020
• intel/cores/ice lake u
  {{comp table header|main|9:Main processor|3:Integrated Graphics}} |theme=vector
  6 KB (810 words) - 23:19, 12 May 2020

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