• cavium/octeon plus/cn5740-900bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5740-1000bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...avium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5734-900bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5740-600bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5740-800bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5740-1000bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...avium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5745-600bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5745-800bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5745-900bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5740-900bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5745-1000bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...avium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5745-600bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5745-800bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5745-900bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 900 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5750-800bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5750-600bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5750-900bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5750-1000bg1217-ssp
  |package module 1={{packages/cavium/fcbga-1217}} ...avium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (419 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5750-600bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017
• cavium/octeon plus/cn5750-800bg1217-sp
  |package module 1={{packages/cavium/fcbga-1217}} ...ium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators spe
  4 KB (398 words) - 16:12, 13 December 2017

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