Semiconductor & Computer Engineering
From WikiChip
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| Date | Name | Thumbnail | Size | Description | Versions |
|---|---|---|---|---|---|
| 13:02, 20 February 2019 | neoverse n1 pipeline.svg (file) |  |
53 KB | Arm {{arm|Neoverse N1|l=arch}} pipeline diagram by WikiChip. | 1 |
| 13:02, 20 February 2019 | neoverse n1 soc block diagram.svg (file) |  |
204 KB | Arm {{arm|Neoverse N1|l=arch}} SoC block diagram by WikiChip. | 1 |
| 12:55, 20 February 2019 | neoverse n1 block diagram.svg (file) |  |
125 KB | Arm {{arm|Neoverse N1|l=arch}} block diagram. | 1 |
| 12:44, 20 February 2019 | neoverse n1 core die plot.png (file) |  |
2.02 MB | Arm {{arm|Neoverse N1|l=arch}} core die plot. | 1 |
| 14:24, 19 February 2019 | xeon e naming scheme.svg (file) |  |
12 KB | 2 | |
| 02:35, 19 February 2019 | mars ii soc block diagram.svg (file) |  |
118 KB | 2 | |
| 02:30, 19 February 2019 | mars ii panel block diagram.svg (file) |  |
24 KB | Phytium {{phytium|Mars II|l=arch}} panel block diagram by WikiChip. | 1 |
| 02:02, 19 February 2019 | mars ii panel (annotated).png (file) | .png) |
273 KB | corrected annotation | 3 |
| 01:54, 19 February 2019 | mars ii panel.png (file) |  |
252 KB | Phytium {{phytium|Mars II|l=arch}} panel. | 1 |
| 01:44, 19 February 2019 | mars ii fcbga-3576.png (file) |  |
3.47 MB | Phytium {{phytium|Mars II|l=arch}} package. | 1 |
| 01:08, 19 February 2019 | ft-2000+-64 (back).png (file) | .png) |
882 KB | FT-2000+/64, back. | 1 |
| 01:08, 19 February 2019 | ft-2000+-64 (front).png (file) | .png) |
396 KB | FT-2000+/64, front | 1 |
| 18:33, 18 February 2019 | mars ii die 2.png (file) |  |
1.88 MB | Phytium {{phytium|Mars II|l=arch}} die. | 1 |
| 18:29, 18 February 2019 | mars ii die (annotated).png (file) | .png) |
1.7 MB | Phytium {{phytium|Mars II|l=arch}} die. Annotated by WikiChip. | 1 |
| 18:29, 18 February 2019 | mars ii die.png (file) |  |
1.81 MB | Phytium {{phytium|Mars II|l=arch}} die. | 1 |
| 17:44, 18 February 2019 | sdm712-brief.pdf (file) |  |
4.42 MB | Qualcomm Snapdragon 712 PB. | 1 |
| 04:32, 10 February 2019 | nersc-9.png (file) |  |
123 KB | NERSC-9 | 1 |
| 05:54, 4 February 2019 | nersc-10.png (file) |  |
129 KB | {{sc|NERSC-10}} | 1 |
| 05:41, 4 February 2019 | nersc-10 roadmap.png (file) |  |
1 MB | {{sc|NERSC-10}} roadmap. | 1 |
| 19:20, 31 January 2019 | large sram blocks highlighted.png (file) |  |
5.58 MB | 2 | |
| 11:50, 31 January 2019 | ayar labs logo.svg (file) |  |
3 KB | Ayar Labs logo | 1 |
| 01:02, 31 January 2019 | 360mm2 wafer yield 0.05pcm2.svg (file) |  |
63 KB | 2 | |
| 18:00, 29 January 2019 | 14nm improv 10 delays.svg (file) |  |
24 KB | Intel 14nm to 10nm roadmap improvision due to delays. | 1 |
| 16:45, 29 January 2019 | sunny cove roadmap.png (file) |  |
1.46 MB | Intel Sunny Cove and onward roadmap | 1 |
| 23:06, 28 January 2019 | 360mm2 wafer example.svg (file) |  |
324 KB | 360 mm2 wafer yield example with chiplets. | 1 |
| 19:11, 28 January 2019 | chiplet design.svg (file) |  |
14 KB | chiplet-based design. | 1 |
| 16:08, 28 January 2019 | monolithic design vs chiplet yield.png (file) |  |
119 KB | Yield for monolithic design vs chiplets for a D0 = 0.1. | 1 |
| 13:09, 28 January 2019 | amd iedm 2017 dr lisa su keynote 7nm cost.png (file) |  |
347 KB | IEDM 2017 AMD Dr. Lisa Su keynote. Cost per yielded mm2 for a 250mm2 die. | 1 |
| 04:49, 28 January 2019 | wafer yield.svg (file) |  |
14 KB | 2 | |
| 01:35, 28 January 2019 | sac cap.svg (file) |  |
10 KB | self-aligned contact capacitance | 1 |
| 00:54, 28 January 2019 | intel 22nm sac yield improvement.png (file) |  |
141 KB | Intel 22 nm process yield improvement due to SAC and contact misalignment. | 1 |
| 21:21, 27 January 2019 | intel 22nm sac.png (file) |  |
18 KB | Intel 22 nm process self-aligned contact. Image by Intel. | 1 |
| 21:20, 27 January 2019 | intel 22nm sac (annotated).png (file) | .png) |
37 KB | Intel 22 nm process self-aligned contact. Image by Intel. Annotated by WikiChip. | 1 |
| 03:26, 27 January 2019 | cpp sac flow.svg (file) |  |
22 KB | Intel's SAC flow. | 1 |
| 02:50, 27 January 2019 | cpp scaling with sac.svg (file) |  |
22 KB | CPP scaling with self-aligned contact. | 1 |
| 02:42, 27 January 2019 | cpp scaling.svg (file) |  |
21 KB | 2 | |
| 00:28, 27 January 2019 | intel scaling roadmap to 5nm.png (file) |  |
1.14 MB | Intel {{intel|Process}} scaling to 5nm. | 1 |
| 00:03, 27 January 2019 | intel 22nm gate.png (file) |  |
243 KB | Intel 22nm transistor gate | 1 |
| 23:41, 26 January 2019 | intel process naming scheme.svg (file) |  |
10 KB | Intel {{intel|Process}} naming scheme. | 1 |
| 23:46, 16 January 2019 | nec sx-aurora cow wafer.png (file) |  |
403 KB | NEC {{nec|SX-Aurora|l=arch}}. Image by NEC. | 1 |
| 23:46, 16 January 2019 | nec sx-aurora chip.png (file) |  |
365 KB | NEC {{nec|SX-Aurora|l=arch}}. Image by NEC. | 1 |
| 23:25, 16 January 2019 | nvidia pascal p100.jpg (file) |  |
55 KB | Nvidia {{nvidia|Pascal|l=arch}} CoWoS. | 1 |
| 23:25, 16 January 2019 | nvidia p100.png (file) |  |
215 KB | Nvidia {{nvidia|Pascal|l=arch}} Nvidia P100 | 1 |
| 01:23, 14 January 2019 | m3 soc block diagram.svg (file) |  |
21 KB | Samsung {{samsung|M3|l=arch}} SoC block diagram. | 1 |
| 00:58, 14 January 2019 | m4 data cache.svg (file) |  |
13 KB | Samsung {{samsung|M4|l=arch}} memory subsystem. | 1 |
| 00:50, 14 January 2019 | m4 fp eu pipes changes.svg (file) |  |
57 KB | Samsung {{samsung|M4|l=arch}} EU pipes changes. | 1 |
| 00:42, 14 January 2019 | m3 fp eu pipes changes.svg (file) |  |
40 KB | Samsung {{samsung|M3|l=arch}} changes. | 1 |
| 00:41, 14 January 2019 | m3 fp scheduler.svg (file) |  |
31 KB | fixed colors | 4 |
| 00:36, 14 January 2019 | mongoose 1 block diagram.svg (file) |  |
98 KB | 8 | |
| 00:34, 14 January 2019 | mongoose 2 block diagram.svg (file) |  |
97 KB | 2 |
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