• movidius/microarchitectures/shave v2.0
  === Instruction Set === ** Instruction predication
  12 KB (1,749 words) - 19:05, 20 January 2021
• cavium/microarchitectures/vulcan
  ** Double fetch throughput (4, up from 2) *** Dedicated instruction TLB
  17 KB (2,449 words) - 22:11, 4 October 2019
• arm holdings/microarchitectures/cortex-a76
  *** Decoupled from the instruction fetch *** Strictly inclusive of the L1 data cache & non-inclusive of the L1 instruction cache
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  ** 1.5x wider instruction fetch (6 instrs/cycle, up from 4) ** 1.5x wider instruction fetch (6 instrs/cycle, up from 4)
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  ** Additional instruction fusion cases **** New packaging scheme (improve instruction density)
  21 KB (3,067 words) - 09:25, 31 March 2022
• intel/microarchitectures/sunny cove
  Sunny Cove TLB consists of a dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is ...hereby variable-length [[x86]] instructions are fetched from the [[level 1 instruction cache]], queued, and consequently get decoded into simpler, fixed-length [[
  34 KB (5,187 words) - 06:27, 17 February 2023
• arm holdings/microarchitectures/arm9/pr1
  ...quires no address translation and contains eight individually programmable instruction and data protection regions. These can be specified as to base address, reg * ARM9TDMI includes 5-stage pipeline (fetch, decode, shifter/arithmetic logic unit (ALU), cache and write-back), Thumb,
  8 KB (1,261 words) - 22:05, 29 December 2018
• centaur/microarchitectures/cha
  ** Instruction cache *** Instruction ROM
  24 KB (3,792 words) - 04:37, 30 September 2022
• arm holdings/microarchitectures/cortex-m55
  === Fetch & Decode === ...tional ECC support if desired. Each cycle, four bytes are fetched from the instruction cache. There, instructions are pre-parsed and are sent to the decode. Since
  12 KB (1,806 words) - 10:51, 12 January 2021
• arm holdings/microarchitectures/neoverse v1
  *** Faster fetch recovery *** 2x wider decoded instruction fetch (8 instrs/cycle, up from 4 traditional)
  5 KB (748 words) - 16:20, 4 July 2022
• arm holdings/microarchitectures/cortex-a510
  *** Wider fetch (128b/cycle, up from 64b) The Cortex-A510 features an instruction TLB (ITLB) and data TLB (DTLB) which are private to each core and an L2 TLB
  15 KB (2,282 words) - 11:20, 10 January 2023
• alchemy/microarchitectures/au1
  ...or CP3 instructions. All floating-point instructions generate the Reserved Instruction exception, therefore can be emulated in software. Code compression (MIPS16) The <code>WAIT</code> instruction can place the core in one of two low power modes: In IDLE1 mode clocks to a
  13 KB (2,114 words) - 16:00, 17 April 2022

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