This is a string property representing the possible configuration for PCIe lanes that are directly going to the chip in context.

IO Subobject

• PCIe
  • Property:io pcie max lanes
  • Property:io pcie revision
  • Property:io pcie config

Pages using the property "io pcie config"

Showing 25 pages using this property.

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CN5734-800 SSP - Cavium#io +	x4  +, x8  +
CN5734-900 SP - Cavium#io +	x4  +, x8  +
CN5734-900 SSP - Cavium#io +	x4  +, x8  +
CN5740-1000 SP - Cavium#io +	x4  +, x8  +
CN5740-1000 SSP - Cavium#io +	x4  +, x8  +
CN5740-600 SP - Cavium#io +	x4  +, x8  +
CN5740-600 SSP - Cavium#io +	x4  +, x8  +
CN5740-800 SP - Cavium#io +	x4  +, x8  +
CN5740-800 SSP - Cavium#io +	x4  +, x8  +
CN5740-900 SP - Cavium#io +	x4  +, x8  +
CN5740-900 SSP - Cavium#io +	x4  +, x8  +
CN5745-1000 SP - Cavium#io +	x4  +, x8  +
CN5745-1000 SSP - Cavium#io +	x4  +, x8  +
CN5745-600 SP - Cavium#io +	x4  +, x8  +
CN5745-600 SSP - Cavium#io +	x4  +, x8  +
CN5745-800 SP - Cavium#io +	x4  +, x8  +
CN5745-800 SSP - Cavium#io +	x4  +, x8  +
CN5745-900 SP - Cavium#io +	x4  +, x8  +
CN5745-900 SSP - Cavium#io +	x4  +, x8  +
CN5750-1000 SP - Cavium#io +	x4  +, x8  +
CN5750-1000 SSP - Cavium#io +	x4  +, x8  +
CN5750-600 SP - Cavium#io +	x4  +, x8  +
CN5750-600 SSP - Cavium#io +	x4  +, x8  +
CN5750-800 SP - Cavium#io +	x4  +, x8  +
CN5750-800 SSP - Cavium#io +	x4  +, x8  +