This is a string property representing the possible configuration for PCIe lanes that are directly going to the chip in context.

IO Subobject

• PCIe
  • Property:io pcie max lanes
  • Property:io pcie revision
  • Property:io pcie config

Pages using the property "io pcie config"

Showing 25 pages using this property.

View (previous 25 | next 25) (20 | 50 | 100 | 250 | 500)

C
Celeron J4105 - Intel#pcie +	1x4+1x2  +, 4x1  +, 2x1+1x2+1x2  +
Celeron N3000 - Intel#io +	1x4  +, 1x2 + 2x1  +, 4x1  +
Celeron N3010 - Intel#io +	1x4  +, 1x2 + 2x1  +, 4x1  +
Celeron N3050 - Intel#io +	1x4  +, 1x2 + 2x1  +, 4x1  +
Celeron N3060 - Intel#io +	1x4  +, 1x2 + 2x1  +, 4x1  +
Celeron N3150 - Intel#io +	1x4  +, 1x2 + 2x1  +, 4x1  +
Celeron N3160 - Intel#io +	1x4  +, 1x2 + 2x1  +, 4x1  +
Celeron N3350 - Intel#io +	4x1  +, 2x1 + 1x2 + 1x2  +
Celeron N3450 - Intel#io +	4x1  +, 2x1 + 1x2 + 1x2  +
Celeron N4000 - Intel#pcie +	1x4+1x2  +, 4x1  +, 2x1+1x2+1x2  +
Celeron N4100 - Intel#pcie +	1x4+1x2  +, 4x1  +, 2x1+1x2+1x2  +
Celeron P4500 - Intel#io +	1x16  +
Celeron P4505 - Intel#io +	1x16  +, 2x8  +
Celeron P4600 - Intel#io +	1x16  +
Celeron U3400 - Intel#io +	1x16  +
Celeron U3405 - Intel#io +	1x16  +, 2x8  +
Celeron U3600 - Intel#io +	1x16  +
Centriq 2434 - Qualcomm#pcie +	x16  +, x8  +, x4  +
Centriq 2452 - Qualcomm#pcie +	x16  +, x8  +, x4  +
Centriq 2460 - Qualcomm#pcie +	x16  +, x8  +, x4  +
CN5734-1000 SP - Cavium#io +	x4  +, x8  +
CN5734-1000 SSP - Cavium#io +	x4  +, x8  +
CN5734-600 SP - Cavium#io +	x4  +, x8  +
CN5734-600 SSP - Cavium#io +	x4  +, x8  +
CN5734-800 SP - Cavium#io +	x4  +, x8  +