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Alpha 21164 - Microarchitectures - DEC
Edit Values | |
Alpha 21164 µarch | |
General Info | |
Arch Type | CPU |
Designer | DEC |
Manufacturer | DEC, Samsung |
Introduction | January, 1995 |
Process | 0.5 µm |
Core Configs | 1 |
Pipeline | |
Type | Superscalar |
OoOE | No |
Speculative | Yes |
Reg Renaming | No |
Stages | 7-12 |
Decode | 4-way |
Instructions | |
ISA | Alpha |
Cache | |
L1I Cache | 8 KiB/core direct-mapped |
L1D Cache | 8 KiB/core direct-mapped |
L2 Cache | 96 KiB/core 3-way set associative |
L3 Cache | 1-64 MiB/motherboard direct-mapped |
Succession | |
Alpha 21164 was an Alpha microarchitecture designed by DEC and introduced in 1995 as a successor to the Alpha 21064 architecture.
History
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Process Technology
- See also: 0.5 µm process
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Architecture
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Die
- 9,300,000 transistors
- ????? cache
- ????? logic
- 0.5 µm 4 metal layers
- 16.5 mm x 18.1 mm
- 298.65 mm² die size
- PGA-499 package
- 294 signal pins
- 205 power/ground rail pins
References
- Edmondson, John H., et al. "Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor." Digital Technical Journal 7.1 (1995).
- Bowhill, William J., et al. "A 300 MHz 64 b quad-issue CMOS RISC microprocessor." Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International. IEEE, 1995.
Facts about "Alpha 21164 - Microarchitectures - DEC"
codename | Alpha 21164 + |
core count | 1 + |
designer | DEC + |
first launched | January 1995 + |
full page name | dec/microarchitectures/alpha 21164 + |
instance of | microarchitecture + |
instruction set architecture | Alpha + |
manufacturer | DEC + and Samsung + |
microarchitecture type | CPU + |
name | Alpha 21164 + |
pipeline stages (max) | 12 + |
pipeline stages (min) | 7 + |
process | 500 nm (0.5 μm, 5.0e-4 mm) + |