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96-core 6-chiplet 3D stacked MIPS processor - Microarchitectures - CEA Leti
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Revision as of 02:05, 29 February 2020 by David (talk | contribs) (David moved page cea-leti/96-core 6-chiplet mips processor to cea-leti/tsarlet without leaving a redirect: CEA told me there's a name for it...)

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96-Core 6-Chiplet 3D stacked MIPS processor (no actual name was given to the project) was a large-scale high-performance SoC technology demonstration by CEA-Leti. The project comprised 96 MIPS cores built using 6 chiplets 3D stack on an active interposer in order to demonstarte in-package silicon scale-out capabilities with superior inter-chip capabilities while reducing the overall power and production cost.

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