Edit Values
Tremont µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	2019/2020
Process	10 nm
Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Instructions
ISA	x86-64
Extensions	MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA
Cores
Core Names	Elkhart Lake, Skyhawk Lake
Succession
Goldmont Plus Gracemont

Tremont is Intel's successor to Goldmont Plus, a 10 nm microarchitecture for ultra-low power devices and microservers.

Codenames

Platform	Core Name	PCH
	Skyhawk Lake
Jacobsville	Elkhart Lake	Mule Creek Canyon

Brands

This section is empty; you can help add the missing info by editing this page.

Release Dates

This section is empty; you can help add the missing info by editing this page.

Technology

Tremont appears to be planned for Intel's 10 nm process.

Compiler support

Compiler	Arch-Specific	Arch-Favorable
ICC	-march=tremont	-mtune=tremont
GCC	-march=tremont	-mtune=tremont
LLVM	-march=tremont	-mtune=tremont
Visual Studio	/arch:?	/tune:?

CPUID

Core	Extended Family	Family	Extended Model	Model
?	0	0x6	0x8	0x6
	Family 6 Model 134

Architecture

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Goldmont Plus

• Graphics
  • Gen 11

New instructions

Tremont introduced a number of new instructions:

• CLWB - Force cache line write-back without flush
• ENCLV - SGX oversubscription instructions
• CLDEMOTE - Cache line demote instruction
• SSE_GFNI - SSE-based Galois Field New Instructions
• Direct store instructions: MOVDIRI, MOVDIR64B
• User wait instructions: TPAUSE, UMONITOR, UMWAIT
• Split Lock Detection - detection and cause an exception for split locks