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From WikiChip
EPYC 7502P - AMD
Edit Values | |
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General Info | |
Microarchitecture |
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7502p&oldid=92979"
Facts about "EPYC 7502P - AMD"
base frequency | 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
clock multiplier | 25 + |
core count | 32 + |
core family | 23 + |
core name | Rome + |
designer | AMD + |
die count | 5 + |
family | EPYC + |
first announced | August 7, 2019 + |
first launched | August 7, 2019 + |
full page name | amd/epyc/7502p + |
has locked clock multiplier | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
ldate | August 7, 2019 + |
manufacturer | TSMC + and GlobalFoundries + |
market segment | Server + |
max cpu count | 1 + |
max memory | 4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) + |
microarchitecture | Zen 2 + |
model number | 7502P + |
name | EPYC 7502P + |
package | SP3 + and FCLGA-4094 + |
part number | 100-000000045 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
series | 7002 + |
smp max ways | 1 + |
socket | SP3 + and LGA-4094 + |
tdp | 180 W (180,000 mW, 0.241 hp, 0.18 kW) + |
technology | CMOS + |
thread count | 64 + |
turbo frequency | 3,350 MHz (3.35 GHz, 3,350,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |