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Denver µarch
General Info
Arch Type	"CPU"
Designer	Nvidia
Manufacturer	TSMC
Introduction	2014
Process	28 nm, 16 nm
Core Configs	2, 4
Pipeline
OoOE	No
Decode	2-way
Instructions
ISA	ARMv8
Cache
L1I Cache	128 KiB/core 4-way set associative
L1D Cache	64 KiB/core 4-way set associative
L2 Cache	2 MiB/core 16-way set associative

Denver is a CPU microarchitecture from Nvidia, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.

Architecture

	List of all Denver Chips
	Main processor										IGP
Model	Launched	Designer	Family	Process	Core	C	T	L2$	L3$	Frequency	Max Mem	Designer	Name	Frequency
Count: 0

References

• NVIDIA’S FIRST CPU IS A WINNER. Denver Uses Dynamic Translation to Outperform Mobile Rivals. - Linley Gwennap (August 18, 2014)