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CN3850-400 SCP - Cavium
Template:mpu The CN3850-400 SCP is a 64-bit dodeca-core MIPS secure network communication microprocessor (SNP) designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN3850-400 SCP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3850-400 SCP - Cavium#package + |
| base frequency | 400 MHz (0.4 GHz, 400,000 kHz) + |
| core count | 12 + |
| core name | cnMIPS + |
| designer | Cavium + |
| family | OCTEON + |
| first announced | September 13, 2004 + |
| first launched | June 1, 2005 + |
| full page name | cavium/octeon/cn3850-400bg1521-scp + |
| has ecc memory support | true + |
| has hardware accelerators for cryptography | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
| l1i$ description | 64-way set associative + |
| l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| ldate | June 1, 2005 + |
| main image | + |
| manufacturer | TSMC + |
| market segment | Networking + |
| max cpu count | 1 + |
| max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| microarchitecture | cnMIPS + |
| model number | CN3850-400 SCP + |
| name | Cavium CN3850-400 SCP + |
| package | FCBGA-1521 + |
| part number | CN3850-400BG1521-SCP + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| series | CN3800 + |
| smp max ways | 1 + |
| supported memory type | DDR2-800 + |
| technology | CMOS + |
| thread count | 12 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
