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From WikiChip
Kirin - HiSilicon
| Kirin | |
| |
| Kirin Logo | |
| Developer | HiSilicon, ARM Holdings |
| Manufacturer | TSMC |
| Type | System on chips |
| Introduction | 2013 (announced) 2014 (launch) |
| Architecture | Performance mobile ARM SoCs |
| ISA | ARM |
| µarch | Cortex-A7, Cortex-A9, Cortex-A53, Cortex-A72, Cortex-A73 |
| Word size | 32 bit 4 octets , 64 bit8 nibbles 8 octets
16 nibbles |
| Process | 28 nm 0.028 μm , 16 nm2.8e-5 mm 0.016 μm , 10 nm1.6e-5 mm 0.01 μm
1.0e-5 mm |
| Technology | CMOS |
| Clock | 1,200 MHz-2,300 MHz |
| Succession | |
| ← | |
| K3 | |
Kirin is a family of 32-bit and 64-bit mobile ARM performance SoCs introduced by HiSilicon in 2014 as a successor to the K3 series.
Facts about "Kirin - HiSilicon"
| designer | HiSilicon + and ARM Holdings + |
| first announced | 2013 + |
| first launched | 2014 + |
| full page name | hisilicon/kirin + |
| instance of | system on a chip family + |
| instruction set architecture | ARM + |
| main designer | HiSilicon + |
| manufacturer | TSMC + |
| microarchitecture | Cortex-A7 +, Cortex-A9 +, Cortex-A53 +, Cortex-A72 + and Cortex-A73 + |
| name | Kirin + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) + |