Cache

Main article: Sandy Bridge § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 64 KiB 65,536 B 0.0625 MiB L1I$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative   L1D$ 32 KiB 32,768 B 0.0313 MiB 1x32 KiB 8-way set associative write-back L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 8-way set associative write-back L3$ 1.5 MiB 1,536 KiB 1,572,864 B 0.00146 GiB     1x1.5 MiB 12-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1333, DDR3-1066 Supports ECC No Max Mem 16 GiB Controllers 1 Channels 2 Max Bandwidth 19.87 GiB/s 20,346.88 MiB/s 21.335 GB/s 21,335.25 MB/s 0.0194 TiB/s 0.0213 TB/s Bandwidth Single 9.93 GiB/s Double 19.87 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 2.0 Max Lanes: 16 Configuration: 1x16, 2x8, 1x8+2x4

Features

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features