Template:mpu R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a dual-core lock-step Cortex-R7 for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6650 GPU.

This model is an SiP variant of the H3 which include the DDR memory on-package.

Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.

Cache

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 640 KiB 655,360 B 0.625 MiB L1I$ 352 KiB 360,448 B 0.344 MiB 4x48+5x32 KiB     L1D$ 288 KiB 294,912 B 0.281 MiB 9x32 KiB     L2$ 2.5 MiB 2,560 KiB 2,621,440 B 0.00244 GiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4-3200 Supports ECC No Controllers 1 Channels 4 Width 32 bit Max Bandwidth 47.68 GiB/s 48,824.32 MiB/s 51.196 GB/s 51,196.01 MB/s 0.0466 TiB/s 0.0512 TB/s Bandwidth Single 11.92 GiB/s Double 23.84 GiB/s Quad 47.68 GiB/s

Expansions

• PCI Express2.0 (1 lane) x 2 ch
• USB 3.0 Host interface (DRD) × 1 ports (wPHY)
• USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
• SD Host interface × 4 ch (SDR104)
• Multimedia card interface × 2 ch
• Serial ATA interface × 1 ch
• Media local bus (MLB) Interface × 1 ch (3 pin interface)
• Controller Area Network (CAN-FD support) Interface × 2ch
• Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
• SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
• Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
• 32bit timer x 26 ch
• PWM timer × 7 ch
• I2C bus interface × 7 ch
• Serial communication interface (SCIF) × 11 ch
• Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
• Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
• Ethernet controller (IEEE802.3u, RMII, without PHY)
• Digital radio interface (DRIF) × 4 ch

Graphics

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	Integrated Graphics Information
	GPU PowerVR GX6650 Designer Imagination Technologies

Features

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	Supported ARM Extensions & Processor Features
	VFPv4 Vector Floating Point (VFP) v4 Extension NEON Advanced SIMD extension TrustZone TrustZone Security Extensions

Block Diagram

Die Shot

• 16 nm process, CMOS FinFET
• 12.94 mm × 8.61 mm
• 111.36 mm² die size

References

• Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10− 7 random hardware failures per hour reliability." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.