Template:mpu Xeon Gold 5120 is a 64-bit 14-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 2.2 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 896 KiB 917,504 B 0.875 MiB L1I$ 448 KiB 458,752 B 0.438 MiB 14x32 KiB 8-way set associative   L1D$ 448 KiB 458,752 B 0.438 MiB 14x32 KiB 8-way set associative write-back L2$ 14 MiB 14,336 KiB 14,680,064 B 0.0137 GiB     14x1 MiB 16-way set associative write-back L3$ 19.25 MiB 19,712 KiB 20,185,088 B 0.0188 GiB     14x1.375 MiB 11-way set associative write-back