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Celeron 3955U - Intel
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Template:mpu Celeron 3955U is a 64-bit dual-core budget x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2 GHz. The 3955U has a TDP of 15 W with a configurable-down TDP of 10 W. This chip incorporates the HD Graphics 510 GPU operating at 300 MHz with a burst frequency of 900 MHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative
L3$ 2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB

Graphics

Integrated Graphic Information
GPU Intel HD Graphics 510
Displays 3
Frequency 300 MHz
0.3 GHz
300,000 KHz
Max frequency 900 MHz
0.9 GHz
900,000 KHz
Max memory 1700 MiB
1,740,800 KiB
1,782,579,200 B
1.66 GiB
Output DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX 12
OpenGL 4.4
Max HDMI Res 4096x2304 @24 Hz
Max DP Res 4096x2304 @60 Hz
Max eDP Res 4096x2304 @60 Hz

Memory controller

Integrated Memory Controller
Type DDR4-1866, DDR4-2133, LPDDR3-1600, LPDDR3-1866
Controllers 1
Channels 2
Max bandwidth 34,100 MB/s
Max memory 32,768 MB

Expansions

Template:mpu expansions

Features

Template:mpu features

Facts about "Celeron 3955U - Intel"
has featureintegrated gpu +
integrated gpuIntel HD Graphics 510 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory1,700 MiB (1,740,800 KiB, 1,782,579,200 B, 1.66 GiB) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +