ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.

Overview

The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a program counter which is 26 bits in size allowing for an address space of up to 64 MiB of data.

Registers

There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.

Instruction Listing

The ARMv1 is broken down into 2 classes of instruction:

• Load Instructions
• Store Instructions
• Arithmetic Instructions
• Logical Instructions
• Comparison Instructions
• Branch Instructions
• Miscellaneous Instructions

ARMv1 ISA
Mnemonic	Syntax	Description	Action
Load Instructions
LDR	LDR{cond} Rd, address	Load Word	Rd = [address]
LDRT	LDRT{cond} Rd, address	Load Word, User Mode Privilege	Rd = [address]
LDRB	LDRB{cond} Rd, address	Load Byte	Rd = ZeroExtend([address])
LDRBT	LDRBT{cond} Rd, address	Load Byte, User Mode Privilege	Rd = ZeroExtend([address])
LDM	LDM{cond}{type} Rn[!], {reglist}	Load Multiple	addr = Rn for each Rd in {reglist}:      Rd = [addr]      addr += {type}
LDM	LDM{cond}{type} Rn[!], {reglist, PC}	Load Multiple	addr = Rn for each Rd in {reglist}:      Rd = [addr]      addr += {type} R15 = [addr]
Store Instructions
STR	STR{cond} Rd, address	Store Word	[address] = Rd
STRT	STRT{cond} Rd, address	Store Word, User Mode Privilege	[address] = Rd
STRB	STRB{cond} Rd, address	Store Byte	[address][7:0] = Rd[7:0]
STRBT	STRBT{cond} Rd, address	Store Byte, User Mode Privilege	[address][7:0] = Rd[7:0]
STM	STM{cond}{type} Rn[!], {reglist}	Store Multiple	addr = Rn for each Rd in {reglist}:      [addr] = Rd      addr += {type}
STM	STM{cond}{type} Rn[!], {reglist}^	Store Multiple, User Mode Privilege	addr = Rn for each Rd in {reglist}:      [addr] = Rd      Rn += {type}
Arithmetic Instructions
ADC	ADC<cond>{S} Rd, Rn, #imm	Add and carry immed	Rd = Rn + immd + C
ADC	ADC<cond>{S} Rd, Rn, Rm[, <shift>]	Add and carry	Rd = Rn + {shifted Rm} + C
ADD	ADD<cond>S Rd, Rn, #imm	Add immed	Rd = Rn + immd
ADD	ADD<cond>S Rd, Rn, Rm[, <shift>]	Add	Rd = Rn + {shifted Rm}
Logical Instructions
AND	AND<cond>{S} Rd, Rn, #imm	AND immed	Rd = Rn · immd
AND	AND<cond>{S} Rd, Rn, Rm[, <shift>]	AND	Rd = Rn · {shifted Rm}
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
xxxxxxx	xxxxxxxxxxxxxx	xxxxxxxxxx	xxxxxxxxxxxxxxxxx
Comparison Instructions
Branch Instructions
Miscellaneous Instructions