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PEZY-SCnp - PEZY
Template:mpu PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+ (28 nm process).
Architecture
- Main article: PEZY-SC §Architecture
The PEZY-SCnp's architecture is identical to the PEZY-SC.
Cache
PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller | |
Type | DDR4-1866 |
Controllers | 1 |
Channels | 8 |
Bandwidth (single) | 14,933 MB/s |
Bandwidth (dual) | 29,866 MB/s |
Bandwidth (quad) | 59,732 MB/s |
Bandwidth (octa) | 119,464 MB/s |
Expansions
Facts about "PEZY-SCnp - PEZY"
l1$ size | 3,072 KiB (3,145,728 B, 3 MiB) + |
l1d$ description | per 2 processor elements + |
l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ description | per processor element + |
l1i$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l2$ description | per city + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ description | per prefecture + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |