Template:mpu Xeon Gold 6152 is a 64-bit x86 high-performance server docosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6152 operates at 2.1 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.375 MiB 1,408 KiB 1,441,792 B L1I$ 704 KiB 720,896 B 0.688 MiB 22x32 KiB 8-way set associative   L1D$ 704 KiB 720,896 B 0.688 MiB 22x32 KiB 8-way set associative write-back L2$ 22 MiB 22,528 KiB 23,068,672 B 0.0215 GiB     22x1 MiB 16-way set associative write-back L3$ 30.25 MiB 30,976 KiB 31,719,424 B 0.0295 GiB     22x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Controllers 1 Channels 6 Max Bandwidth 119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s Bandwidth Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s